VHDL is the hardware language for FPGA development. The latest generation Xilinx SoC FPGAs has integrated ARM processors and a variety of IP blocks that needs to be controlled and configured via a software-based approach. C/C++ or SystemC languages are used now as the new hardware language for SoC FPGAs. With Vivado High-level Synthesis C code will be converted into a FPGA netlist. This presentation provides a look at how that is done.
Frank de Bont, Core|Vision