Where’s the logic in VHDL verification?

FPGAs are finding their way into in ever increasing number of applications. Modern FPGA’s host ever more complex designs. The verification of these designs is without a doubt a major challenge for FPGA designers. Engineers who use VHDL as their design language most probably also use this for verification. Creating testbenches in VHDL from scratch can be a tedious task. In this talk I will present how to pick a good verification methodology without having a major step in complexity based on experiences with these methodologies in multiple projects as a FPGA designer.

Robert Wijma, Alten

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