The growing number of high-performance FPGA and ASIC applications that are driven by the increased bandwidth of wireless networks and data centers demand for power regulators with high power density, fast load transient response, and high efficiency. Xilinx Zynq UltraScale+ RFSoCs integrate multi-giga-sample RF data converters and soft-decision forward error correction (SD-FEC) into a SoC architecture. Complete with an ARM Cortex-A53 processing subsystem, UltraScale+ programmable logic, and the highest signal processing bandwidth in a Zynq UltraScale+ device, the new family provides a comprehensive RF signal chain for wireless, cable access, test & measurement, early warning / radar, and other high performance RF applications.
Key Specifications:
The current specification of each rail can vary depending upon the part number and specific application/program that will be running on the RFSoC. Table 1 illustrates the typical current requirement of each rail for the Zynq UltraScale+ RFSoC family. It is recommended to use the Xilinx Power Estimation (XPE) tool to estimate the accurate current requirement for optimization of the power solution design. Besides the voltage and current specifications, the power supplies for Xilinx FPGA power rails must meet the following requirements:
• The output voltage ripple of all power rails (except for analog rails) must be smaller than 10mV in steady state.
• The start-up of all power rails must be monotonic.
• Output voltage deviation of the core rail (VCCINT) must be smaller than +- 3% during a 25% load transient at 100A/μs.
• The turn-on and turn-off of the power supplies must follow a certain sequence defined by Xilinx.
