The Importance of Layout in ESD Suppressing Diodes

By Aziz Yuldashevm, courtesy of Interference Technology.

ESD protection of sensitive electronics via transient voltage suppression (TVS) diodes is becoming a common circuit technique across industries. Signal lines in a circuit that are accessible to humans by touch (such as USB, HDMI, etc.) require ESD protection on all sensitive signal lines that are input to some IC’s. Placement of the ESD protection diodes on the circuit board relative the IC’s they are protecting play a significant role. It is important to understand the behavior of PCB traces of signals at transient conditions such as ESD. As an example, a simple schematic of an I2C bus extender with TVS diodes is shown in Figure 1.

The realistic model of this circuit at transient ESD is shown in Figure 2.

PCB traces will have inductances associated with them based on their length. Consider the SDA signal trace. Trace lengths connecting the following points are very important:

• The trace length from node A to the cathode of the diode.
• The trace length from the anode of the diode to the ground connection.
• The trace length from node A to the input pin of the IC.

In other words, the ESD protection diode must be placed as close to the pin that it is protecting as possible and its connection to the reference plane must be made as close to the anode pin as possible. Otherwise the trace inductance between any of these points may be large enough that due to the input capacitance of the IC and the stray capacitance of the trace, a tank circuit may form. The tank circuit may oscillate at voltages that can exceed the input voltage capability of the IC and can cause substantial damage to the IC.

This scenario was modeled in LTSpice. Figure 3 shows the schematic created in LTSpice. It consists of two parts. The first part is the Human body model for ESD based on IEC 61000-4-2 test method. The second part is the representation of Figure 2 for trace SDA. The Figure 3 representation is for a diode (10Vclamp) that was placed properly with very short traces at all points listed above, thus resulting in very small trace inductances. Figure 4 shows the voltage at the CMOS based input (represented by a capacitor).

Figure 6 clearly shows the effect of long traces connecting the diode cathode to the node of the signal line and the diode anode to the ground. The oscillation observed peaks at 21V and rings at the frequency dictated by the trace inductance, stray capacitance of the line and the input capacitance of the IC.

Conclusion

To minimize oscillations on I/O lines due to ESD and to avoid IC damage, the following must be assured:

• Clamping (TVS) diode must be placed as close to the IC pin as possible.
• The trace leading to the cathode of the diode must be as short as possible.
• The trace leading to ground return from the anode of the diode must be as short as possible.

Read there original article here.